1. Field of the Invention
This invention relates to a method of removing a silicon nitride (Si.sub.3 N.sub.4) material, and more particularly to a method with an etchant recipe to remove a silicon nitride layer within a contact opening on a gate, in which the silicon nitride layer is used as a cap on the gate of a transistor.
2. Description of Related Art
Silicon nitride is a typical dielectric material widely used in semiconductor fabrication because it has a high density and strong hardness. Due its high density, silicon nitride can resist water vapor and alkaline ions, so it is commonly used to form a mask layer in a local oxidation process to pattern out a region such as an active region. It is also used to form a passivation layer to prevent mechanical damage or an oxidation on device elements from occurring. Furthermore, silicon nitride can also be used to form a side-wall and a cap on a gate of a metal oxide semiconductor (MOS) transistor.
A silicon nitride layer is usually formed by either a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced CVD (PECVD) process. The LPCVD process is performed by making use of a reaction between dichlorosilane (SiH.sub.2 Cl.sub.2) gas and ammonium (NH.sub.3) gas to produce silicon nitride vapor, which is then deposited. The required conditions of the reaction environment are a temperature of about 700-800.degree. C. and a pressure of about 0.1-1 torr. Since the temperature needed for LPCVD is too high, the device elements may be damaged. An alternative process is PECVD, which needs a lower temperature of about 250-400.degree. C. because the reaction gas is SiH.sub.4 gas instead of SiH.sub.2 Cl.sub.2 gas. The PECVD also produces a lower tensile stress so that it allows a formation of a thicker silicon nitride layer.
Even though silicon nitride can be used to cover device elements such as a cap and a side-wall on the gate of the MOS transistor mentioned above, it makes it difficult to form a contact opening on it by etching through the silicon nitride layer. It is especially difficult to form a contact opening in a peripheral region in a dynamic random access memory (DRAM) fabrication process, in which the distance between interconnect lines is as small as about 0.25 microns.
FIGS. 1A-1C are cross-sectional views schematically illustrating a conventional fabrication flow of a contact opening on a MOS transistor in a peripheral region of a semiconductor substrate. In FIG. 1A, a,MOS transistor with a gate 102 and two interchangeable source/drain regions 103 are formed in a peripheral region 105 on a semiconductor substrate 100. There is a side-wall 104 on each side of the gate 102 and a cap 106 on the top of the gate 102. Both the side-wall 104 and the cap 106 are made of, for example, silicon nitride. Since formation of a DRAM in a DRAM fabrication region (not shown) needs several depositions of oxide, an oxide layer 108 with a great thickness is accumulatively deposited over the substrate 100 in the peripheral region 105 of the DRAM fabrication region. In FIG. 2B, an etching process is performed to form a trench 114 to expose the cap 106 on the gate 102, in which process the etchant is a mixed plasma gas of C.sub.4 F.sub.8 /CO/Ar/O.sub.2.
In FIG. 1B and FIG. 1C, a plasma etching is subsequently performed to etch out the cap 106 within the trench 114 to form a contact opening 112, which exposes the gate 102. The plasma ion gas for this PECVD process is, for example, CF.sub.4, CHF.sub.3, or any other gas containing fluorine.
The conventional method of removing silicon nitride, using a single recipe of fluoric gas as etchant, has a very poor effect. This is because of a poor etching selectivity. During plasma etching, the nitrogen atoms in the cap 106 and the silicon atoms in substrate 100 can form Si--N bonds, which have a strength between that of Si--O bonds and Si--Si bonds. If a single fluoric plasma gas, such as CF.sub.4 or fluoroform CHF.sub.3, is used as the etchant, the etching selectivity is poor. For example, the CHF.sub.3 etchant has an etching selectivity of about 10 or more for silicon oxide to silicon but about 3 to 5 for silicon nitride to silicon, and about 2 to 4 for silicon nitride to silicon oxide. When the contact opening 116 is formed by etching, the opening bottom 116, which is the top of gate 102 and is usually made of polysilicon, is also etched a little. This causes an increase of contact impedance on the gate 102.